With the scaling down of semiconductor devices, short channel effects become increasingly significant. In order to suppress the short channel effects, Fin Field Effect Transistors (FinFETs) formed on SOI wafers or bulk semiconductor substrates have been proposed. The FinFET comprises a channel region formed in a central portion of a fin of semiconductor material and source/drain regions formed at opposite ends of the fin. A gate electrode is provided on opposite sides of the channel region to surround the latter (i.e., a double-gate configuration), in which an inversion layer is formed at each side of the channel. As the whole channel region can be controlled by the gate, the short channel effects can be suppressed.
When being lot-produced, FinFETs manufactured by using bulk semiconductor substrates have higher cost efficiency than those manufactured by using SOI wafers and thus are widely used. For a FinFET using a semiconductor substrate, however, it is difficult to control the height of the semiconductor fin, and a conductive path may be formed between the source region and the drain region via the semiconductor substrate, causing a problem of leakage current.
In order to reduce the leakage current between the source region and the drain region, a doped punch-through-stopper layer may be formed under the semiconductor fin. For example, the doped punch-through-stopper layer is provided by forming a doped region through ion implantation into the semiconductor substrate, and then a portion of the semiconductor substrate disposed above the doped punch-through-stopper layer is patterned into the semiconductor fin.
However, it is difficult to form a clear boundary for the doped region due to the concentration distribution of the doped region. It is difficult to well define the position in depth and thickness of the punch-through-stopper layer provided by the doped region. It is also difficult to well define the thickness of the semiconductor fin above the doped punch-through-stopper layer. A transition area between the semiconductor fin and the doped punch-through-stopper layer may become a potential leakage current path and cause undesired random change in the threshold voltage of the FinFET.